Micron is a global leader in NAND technology, pushing the boundaries of semiconductor possibilities. As the Lead (SMTS/Sr. Mgr) of NAND CMOS Team, you will be responsible for the introduction and ramp of ALL NAND products in Singapore, and ensure that all CMOS Device aspects (time-0 and Reliability) are fulfilled with highest quality. You will ensure that all Device VDLs are monitored on a weekly basis, manage a Device Health dashboard (time0 and REL), and provide direction on device optimization/centering to ensure all downstream product requirements are fulfilled on-time.
Leader Responsibilities:
- Ensure that all CMOS VDLs meet Device Maturity Index (DMI) requirements.
- Be the Electrical-SPEC (ESPEC) gate-keeper across all NAND CMOS technologies (through process conversions), and ensure high confidence ESPEC compliance is maintained throughout.
- Manage & Maintain ESPEC spec-source and ensure that performance is compliant with PDK commit. If issues arise, work closely with Design for DTCO containment.
- Have in-depth understanding and ensure full compliance to all key business processes (ESPEC, DTCO, FMEA, DMI, etc..)
- Have in-depth understanding of circuit usage/fail modes (for every VDL), and be able to understand Live-Die vs. Param layout differences.
- Have in-depth understanding of NAND Voltage Spec (VSPEC) document, and ensure that you work with partner Produce & Quality organizations to guarantee 0 VSPEC violations through all end-2-end test methodologies (Probe, Qual flows).
- You will work closely with Device Reliability teams to enable fast reliability flows, towards establishment of continuous line monitor of REL health.
- You will engage seamlessly with the CMOS Process Integration and Device Technology Teams, and foster a One-Team culture always.
- For every Device issue, you will inculcate an FMEA-first and TCAD-first mindset, before deploying silicon solutions.
- Develop a culture of excellence, psychological safety, inclusion, and engagement.
- Continuously improve CMOS team technology approaches and business processes to meet customer needs and adapt to the changing landscape.
- Implement project management best known methods (BKMs) to coordinate activities and deliver projects on schedule.
- Drive effective multi-functional collaboration with internal customers (design, PE, etc.) and partners (integration, process, scribe, modeling, etc.).
- Negotiate and clarify roles and responsibilities with all partner organizations.
- Summarize complex problems and communicate solutions and execution plans to executive leadership.
- Maintain seamless communication between all departments and sites across organizational borders.
Qualifications:
- MS degree or PhD with 7-10+ years of DRAM and/or NAND research and development experience.
- Proven capability to deliver novel technology solutions and successfully resolve complex issues that span multiple groups.
- Proven ability to think and communicate clearly in urgent and stressful situations.
- Strong background in CMOS integration, scaling, and device physics.
- Deep knowledge of Design of Experiments (DOE) principles and analytical skills.
- Innovation track record with a proactive approach to exploring new ideas and adapting quickly to change.