MTS-HIG-HBM-PE-COMPONENT-VAL

Key Responsibilities

• Validation Execution & Coverage

• Plan and execute Validation Runs: define coverage, select flows (VALDOT, VALBBC, VALASC, VALRHR, VALCHAR, VALV2V), and deliver high-quality summaries and sightings.

• Drive Hot/Cold corner testing, TSV screen/AQLK, and async timing boundary coverage to close functional/timing/stress gaps.

• Technical Excellence (Core IC Focus)

• High-Speed I/O Validation Leadership:

• Validate ultra-high-speed interfaces at 11Gbps+; perform eye diagram quality assessment, jitter analysis, and signal integrity validation across voltage/temperature/process corners.

• Expand speed grades and shmoo ranges for CS/QS phases; define acceptance thresholds and margining strategies.

• Power and Thermal Characterization:

• Measure and optimize IDD profiles, thermal behavior, and energy efficiency under realistic workloads and environmental stress.

• Build models correlating IDD/thermal data with performance and reliability; recommend test content changes and silicon fixes.

• Comprehensive Coverage Planning:

• Architect coverage across MBIST and Native Mode ensuring no gaps in functional/timing/stress conditions.

• Own execution fidelity for ValRuns across flows, including log review, pattern sensitivity analysis, corner completeness, and AQLK compliance.

• Multi-Platform Test Enablement:

• Develop, port, and debug test programs on SM3.5 Cobra (MBIST) and Advantest V93K (Native); ensure hardware configs (handler, socket, loadboard, probe card) are aligned with test intent.

• Collaborate on Teradyne UltraFlex ETV strategy: enable partner IP patterns, dual cube/die validation, and targeted Rev flows.

• Data-Driven Validation:

• Build automated pipelines for log parsing, data crunching, statistical anomaly detection, and trend dashboards using Python/Perl and modern analytics.

• Maintain validation artifacts in Confluence/Jira; version test code/content in Git/Perforce with branching/release discipline.

• Quality & Continuous Improvement:

• Codify the “Definition of Success” for component validation; lead DFMEA gap closure and learning cycles that reduce IQP dependency while increasing early detection.

• Propose and implement cycle-time improvements (e.g., parallelization, smarter sampling, content pruning with evidence).

• Innovation & Future Readiness:

• Prototype automation and AI/ML-driven analytics (e.g., classifier-based sighting triage, predictive margining, outlier detection) to boost throughput and detection efficiency.

• Anticipate requirements for HBM4E and beyond; author technical roadmaps for speed, power, reliability, and platform capabilities.

• Root Cause Analysis & Debug

• Lead silicon issue triage; reproduce, localize, and isolate root causes; recommend corrective actions spanning design edits, test content, and platform setup.

• Drive cross-functional debug with Design, Verification, Quality, System Engineering; document findings and closure evidence.

• Global Collaboration

• Partner with Boise, Folsom, Hyderabad, and Taiwan teams for material readiness, platform enablement, handler/sockets/loadboard readiness, and joint debug; share best practices and playbooks.

Minimum Qualifications

• Master’s in Electrical or Computer Engineering (or related).

• 10+ years in DRAM/HBM/NAND product or validation engineering with deep, hands-on experience across MBIST and Native Mode testing. At least 2 years of HBM Validation experience.

• Expertise in SM3/Cobra code flows and Advantest V93K program development/debug; Teradyne UltraFlex exposure preferred.

• Proven execution of Validation Runs on IQP/ETV materials: coverage definition, Hot/Cold corners, TSV screen/AQLK, and sighting closure.

• Strong command of HBM datasheet functions, interface timing, and component-level coverage.

• Demonstrated success in high-speed (>11Gbps) I/O validation, eye/IDD characterization, and performance optimization in CS/QS environments.

• Proficiency in Python/Perl scripting, data pipelines, and analytics; experience with Confluence/Jira and Git/Perforce.

Preferred Qualifications

• Track record in Rev flow development, CS/QS shmoo targets, and async timing boundaries coverage.

• Experience coordinating ETV/dual cube/die validation and enabling partner IP patterns on UltraFlex.

• Contributions to DFMEA gap closure, zero-miss charter alignment, and formal “Definition of Success” frameworks.

• Hands-on development of automation or ML-based validation analytics (e.g., anomaly classifiers, trend predictors).