Senior Engineer, Process Development, CMP & Wafer Thinning

As a Process and Equipment Development Engineer in the NAND CMP and wafer thinning R&D team, you will be primarily responsible for developing and optimizing wafer thinning processes (grind, trim, and CMP processes) and equipment to improve product quality and reliability for the next generation of Micron's memory parts. You will take ideas from conception, through process development, all the way to implementation in our production facilities. You will also be required to identify, diagnose, and resolve assembly process related problems by applying failure analysis, FMEA, 8D or SPC/FDC methodology. Additional responsibilities include coordinating and carrying out process, equipment, and material evaluation/optimization to implement changes at process step, leading and participating in yield improvement and cost reduction activities, handling new process baseline qualifications, and managing, auditing, and liaising with material suppliers to achieve quality, cost, and risk management objectives.

At Micron, we tackle challenging tactical and technical problems to meet the demands of our fast-paced and dynamic development environment. You will be working in a highly collaborative atmosphere, interacting with various groups such as process integration, electrical failure analysis, yield enhancement, manufacturing, and equipment vendors, to ensure robust processes that meet the detailed physical and electrical requirements for Micron products. You will grow into an expert engineer, driving wafer thinning technology roadmaps, which have a direct influence on Micron’s global leadership in semiconductor manufacturing.

Responsibilities include, but not limited to:

• Developing wafer thinning and edge trim processes and equipment to meet the physical and electrical requirements of Micron’s products.
• Developing CMP processes to meet product and module requirements
• Optimizing processes and equipment to reduce cost, process variability, and improve process capability.
• Collaborating with process integration and other process development teams to develop innovative new solutions.
• Conducting root cause and failure mode analysis to understand the limitations of current hardware and drive thinning development projects with OEMs vendors for solutions.
• Develop hardware and process roadmaps for 5+ years in wafer thinning and CMP (including grinding, trim and CMP).
• Performing fundamental research to drive innovative solutions for next-generation products.
• Maintaining a technology development pilot manufacturing line.
• Support process and equipment transfer to production facilities (some international travel may be required).

Minimum Qualifications:

• Experience with design of experiment techniques (DOE), Statistical Process Control (SPC), Defect analysis and data analysis
• Strong analytical and creative problem-solving skills.
• Ability to use extensive technical knowledge to guide strategic directions.
• Ability to resolve complex issues through root-cause or model-based problem solving.
• Proficiency in statistics, preferably in statistical process control.
• Ability to work independently, with minimal direction, and a focus on meeting commitments.
• Ability to multi-task and manage numerous projects simultaneously.
• Hands on experience with wafer thinning tools and edge trim tools.

Education and Experience.

• M.S./Ph. D. (or equivalent education) in Materials Science, Chemical Engineering, Electrical Engineering, Mechanical Engineering, Chemistry, Physics, or other related technical fields.
• Ideal candidate will have 3 to 5+ years of semiconductor process engineering experience across wafer thinning, packaging and CMP related processes preferably in 300mm wafer fab.
• Experience in thinning, trim and CMP process development with fundamental understanding of process and equipment interactions.
• Experience in wafer thinning and edge trim process development and understanding of thinning, edge trim and CMP related inline/electrical/probe failure.
• Knowledge of semiconductor processing, solid-state device physics desirable.